(1) Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a split-gate flash memory cell having a protruding source, and also to a method of forming the same. The protruding source increases the coupling ratio between itself and the floating gate while decreasing the coupling between the floating gate and the control gate, thereby improving the over-all erasing and programming speed of the newly disclosed flash memory cell.
(2) Description of the Related Art
Conventionally, and as it will be described in more detail later, voltage coupling between the source and the floating gate of a memory cell is achieved by providing an overlap through lateral diffusion of source implant species in the source region of the substrate. Source region is usually flat and the overlap with the floating gate is usually imprecise and not amenable to shrinking of the size of the cell for the ever increasing demands of the ultra scale integration (ULSI) of circuits. There is also the usual problem of voltage punch-through between the flat source and the drain of a cell. It is disclosed later in the embodiments of the present invention a cell structure with a protruding source which alleviates these problems.
A method of forming a conventional split-gate flash memory cell is shown in FIG. 1a where a layer of gate oxide (30) is thermally grown over substrate (10). Next, a first polysilicon layer (40) is formed followed by the deposition of nitride layer (50). A photoresist layer (60) is then spun over the substrate and then patterned with a floating gate pattern as shown in FIG. 1b, which in turn, is etched into the nitride layer (50) as shown in FIG. 1c. The photoresist layer, which is no longer needed, is removed. Next, the first polysilicon that is exposed in the pattern openings in the nitride layer is oxidized to form polyoxide (45) as shown in FIG. 1d. Subsequently, the nitride layer is removed where now polyoxide (45) serves as a hard mask to remove all the first polysilicon portions except those that are covered by the polyoxide (FIG. 1e). As is well known in the art, this is usually accomplished by main etch followed by over-etch. It is at this etching step that the corner edge (47) is usually rounded off, as seen in FIG. 1e, which is not desirable for achieving fast program erase speed described below. It will be shown later in the embodiments of this invention that the sharpness of corner edge (47) can be improved such that charge transfer between substrate (10) and floating gate (40), and then the charge transfer between the floating gate and control gate, (60), is fast. The control gate is formed by depositing a second polysilicon layer over intergate layer (50), also known as interpoly, which separates the two polysilicon layers, namely, the floating polygate and the control polygate. The completed split-gate cell structure is shown in FIG. 1f. 
Over the years, numerous improvements in the performance as well as in the size of memory devices have been made by varying the simple, basic one-transistor memory cell, which contains one transistor and one capacitor. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines. In general, memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Many types of memory cells for EEPROMs or flash EEPROMs may have source and drains regions that are aligned to a floating gate or aligned to spacers. When the source and drain regions are aligned to the floating gate, a gate electrode for a select transistor is separate from the control gate electrode of the floating gate transistor. Separate select and control gates increase the size of the memory cell. If the source and drain regions are aligned to a spacer formed after the floating gate is formed, the floating gate typically does not overlie portions of the source and drain regions. Programming and erasing performance is degraded by the offset between the floating gate and source and drain regions.
FIG. 1g, which is an enlarged view of FIG. 1f, is a conventional flash-EEPROM cell where two MOS transistors share a common source (25). A top view is shown in FIG. 1h. FIG. 1g is a cross-sectional view of the cell taken at 1gxe2x80x941g crossing active region (15) defined by passive filed oxide or isolation region (13). A top view of the shared common source line is referenced as (70) in FIG. 1h. 
In the cross-sectional view 1g, the first doped region, (20), lies within the substrate. The second doped region, (25), also lies within substrate (10) and is spaced apart form the first doped region (20). Channel region (23) lies within substrate (10) and between first (20) and second (25) doped regions. Gate oxide layer (30) overlies substrate (10). Floating gate (40), to which there is no direct electrical connection, and which overlies substrate (10), is separated from substrate (10) by a thin layer of gate oxide (30) while control gate (60), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (50) therebetween.
To program the transistor shown in FIG. 1g, charge is transferred from substrate (10) through gate oxide (30) and is stored on floating gate (40) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed xe2x80x9conxe2x80x9d of xe2x80x9coff.xe2x80x9d xe2x80x9cReadingxe2x80x9d of the cell""s state is accomplished by applying appropriate voltages to the cell source (25), Vs, drain (20), Vd, and to control gate (60), Vg, and then sensing the amount of charge on floating gate (40). To erase the contents of the cell, charges are removed from the floating gate by transferring them to the word line (control gate) through the gate oxide. The path of the charge transfer is shown by arrows (41) in FIG. 1g. 
This programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim (FN) tunneling for erasing, and channel-hot electron (CHE) injection for programming, as is well known in the art. FN tunneling usually requires higher voltage than the CHE mechanism. It is common practice use FN tunneling for both write and erase for NAND type of cell architecture, while CHE programming and FN tunneling erasure is used for NOR circuits. The latter approach is shown in FIG. 1g. Thus, in the programming mode, source (25) is coupled to the floating gate through a high voltage which in turn creates a high electric field between floating gate (40) and control gate (60), thereby causing injection of CHEs from substrate (10) to floating gate (40) in FIG. 1g. In the erase mode, on the other hand, the control gate is impressed with a high voltage and electrons are injected from the floating gate to the control gate through the FN tunneling mechanism, usually aided by the poly tip of the floating gate.
Erasing and programming speed of a split gate flash memory cell is governed by the capacitive coupling between different parts of the cell. As it will be described more fully later, the programming and erasing of the cell is accomplished by transferring charges between polysilicon or poly parts comprising the floating gate, control gate and the source region in the device substrate. A faster erase speed is achieved if the coupling ratio between the control gate and the floating gate is low, which in turn, is attained by having a thinner floating gate as well as a sharper edge on the gate. With conventional methods of forming split gate cells, it is difficult to have low coupling ratio because of the relatively tall sidewalls of the floating gate. This is compensated to a large extent by forming a sharp edge or tip on the floating gate. On the other hand, higher programming speed is achieved if the coupling ratio between the floating gate and the source region is higher with relatively thicker gate. It is disclosed in the embodiments of the present invention a method of forming a split gate flash memory cell having a thin floating gate and a sharp poly tip in order to improve erasing and programming speed of the cell.
In U.S. Pat. No. 5,879,992, Hsieh, et al., provide a method for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched to form a step adjacent to the side-wall of a floating gate underlying the polyoxide. A spacer is next formed of a hot temperature oxide over the step poly. An interpoly oxynitride is then formed and control gate is patterned overlapping the floating gate with the intervening interpoly oxide. The step poly and the spacer thereon form proper distances between the control gate and the floating gate while keeping the distance between the poly tip and the control gate unchanged so that appropriate couplings between the control gate and the floating gate, and between the floating gate and the substrate are achieved, thus improving the over-all performance of the split-gate flash memory having a step poly.
In another U.S. Pat. No. 5,858,840, Hsieh, et al., propose a method for forming a short and sharp gate bird""s beak in order to increase the erase speed of a split-gate flash memory cell. This is accomplished by implanting nitrogen ions in the first polysilicon layer of the cell and removing them from the area where the floating gate is to be formed. Then, when the polysilicon layer is oxidized to form polyoxide, the floating gate region without the nitrogen ions oxidizes faster than the surrounding area still having the nitrogen ions. Consequently, the bird""s beak that is formed at the edges of the polyoxide assumes a sharper shape with smaller size than that is found in prior art. This results in an increase in the erase speed of the memory cell.
A different method of making a split-gate flash EEPROM cell is disclosed by Chen, et al., in U.S. Pat. No. 5,824,584 where a sidewall select gate is formed in conjunction with a semiconductor doped oxide to form a non-volatile memory cell. The semiconductor element used to dope the oxide layer includes silicon or germanium. The nonvolatile memory cell is programmed by storing electrons in the doped oxide, and is erase using band-to-band tunneling.
Manley in U.S. Pat. No. 5,063,172 provides an integrated circuit fabrication method that utilizes a conductive spacer to define the gate length of the series select transistor in a split-gate memory cell. Since the length of the spacer can be controlled with great precision using existing integrated circuit process technologies, misalignment problems associated with the prior art split-gate cells are eliminated.
In U.S. Pat. 5,915,178 by Chiang, et al., add a shallow source side implanted region in order to improve the endurances of a split gate flash EEPROM device. The process features placing a shallow, ion implanted arsenic region, in the semiconductor substrate, adjacent to one side of a floating gate structure, prior to creation of the control gate structure. The addition of the shallow, ion implanted arsenic region, improves the coupling ratio at the source, which in turn results in the ability of the flash EEPROM device to sustain about 1,000,000 program/erase cycles, compared to counterparts, fabricated without the shallow, source side region, only able to sustain about 400,000 program/erase cycles.
In the present invention that is disclosed later in the embodiments, the flat source of prior art is replaced with a protruding source structure. The protruding source increases the coupling ratio between itself and the floating gate while decreasing the coupling between the floating gate and the control gate, thereby improving the overall erasing and programming speed of the newly disclosed flash memory cell. The cell is further enhanced by employing a spacer control gate, which, together with the protruding source, makes it possible to shrink the cell substantially.
It is therefore an object of this invention to provide method of forming a split-gate flash memory cell having a protruding source in place of the conventional flat source.
It is another object of the present invention to provide a method of forming a split-gate flash memory cell having a thin floating gate and a sharp poly-tip.
It is yet another object of the present invention to provide a method of forming a split-gate flash memory cell having a self-aligned spacer control gate and word line.
It is still another object of the present invention to provide a split-gate flash memory cell with a protruding source structure having a floating gate and a control gate formed vertically around the protruding structure in order to increase the coupling ratio between the source and the floating gate while decreasing the coupling between the floating gate and the control gate, thereby improving the over-all erasing and programming speed of the split-gate flash memory cell.
These objects are accomplished by providing a semiconductor substrate having passive and active regions defined; forming a pad oxide layer over said substrate; forming a nitride layer over said pad oxide layer; forming an opening in said first nitride layer until said substrate is reached to form a source region in said substrate; performing ion implantation to form said source region in said substrate; forming a first polysilicon (Poly-1) layer in said opening to form a protruding source structure over said source region; forming a first poly-oxide layer over said Poly-1 layer; removing said nitride layer on said substrate; removing said pad oxide layer on said substrate; forming a floating gate oxide layer over said substrate, including over said protruding source structure; forming a second polysilicon (Poly-2) layer to form a floating gate over said floating gate oxide layer; removing portions of said Poly-2 layer over said substrate to isolate active regions; forming a second poly-oxide layer over said Poly-2 layer over said substrate including over said protruding source structure by oxidizing an upper portion of said Poly -2 layer while leaving a lower portion of said Poly-2 unoxidized to form said floating gate; removing a portion of said second poly-oxide layer, thus leaving said Poly-2 layer over said substrate partially exposed in regions other than over said protruding source structure; removing said partially exposed Poly-2 layer; forming an inter-gate oxide layer over said substrate; forming a third polysilicon (Poly-3) layer over said inter-gate oxide layer; forming a Poly-3 spacer over said inter-gate oxide layer on the vertical walls of said protruding source structure to form a spacer control gate; and performing ion implantation to form a drain region of said flash cell having said protruding source structure.
These objects are accomplished further by providing a semiconductor substrate having active and passive regions defined; a source region and a drain region within said substrate; a pad oxide layer over said substrate; a protruding source structure with vertical walls having a top portion and bottom portion formed over said source region; a floating gate oxide layer formed over said vertical walls of said protruding source structure; a thin vertical floating gate having a bottom edge over said floating gate oxide; a thin and sharp poly-tip at said bottom edge of said vertical floating gate; an inter-gate oxide over said vertical floating gate, including said sharp poly-tip; and a spacer control gate over said inter-gate oxide layer.